/**
  ******************************************************************************
  * @file    stm32f4x7_eth_conf_template.h
  * @author  MCD Application Team
  * @version V1.1.0
  * @date    31-July-2013
  * @brief   Configuration file for the STM32F4x7xx Ethernet driver.
  *          This file should be copied to the application folder and renamed to
  *          stm32f4x7_eth_conf.h    
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
  *
  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  * You may not use this file except in compliance with the License.
  * You may obtain a copy of the License at:
  *
  *        http://www.st.com/software_license_agreement_liberty_v2
  *
  * Unless required by applicable law or agreed to in writing, software 
  * distributed under the License is distributed on an "AS IS" BASIS, 
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  *
  ******************************************************************************
  */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4x7_ETH_CONF_H
#define __STM32F4x7_ETH_CONF_H

#ifdef __cplusplus
 extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"


/* 使用时间戳和/或IPv4校验和卸载时，请取消对以下行的注释 */
#define USE_ENHANCED_DMA_DESCRIPTORS

/* 使用用户定义的延迟函数 */
#define USE_Delay

#ifdef USE_Delay
  #include "../../../User/Delay/delay.h"
  #define _eth_delay_    WHT_Delay_ms
#else
  #define _eth_delay_    ETH_Delay
#endif

/* 以太网驱动程序缓冲区的配置 */    
#define CUSTOM_DRIVER_BUFFERS_CONFIG   

#ifdef  CUSTOM_DRIVER_BUFFERS_CONFIG
/* 重新定义以太网驱动程序缓冲区的大小和数量 */   
 #define ETH_RX_BUF_SIZE    ETH_MAX_PACKET_SIZE /* buffer size for receive */
 #define ETH_TX_BUF_SIZE    ETH_MAX_PACKET_SIZE /* buffer size for transmit */
 #define ETH_RXBUFNB        8                   /* 20 Rx buffers of size ETH_RX_BUF_SIZE */
 #define ETH_TXBUFNB        4                   /* 5  Tx buffers of size ETH_TX_BUF_SIZE */
#endif


/****************** PHY 配置部分 *********************************/
#ifdef USE_Delay
/* PHY 复位延迟 */ 
#define PHY_RESET_DELAY         ((uint32_t)0x00000005)
/* PHY 配置延迟 */
#define PHY_CONFIG_DELAY        (PHY_RESET_DELAY*2)
/* 写入以太网寄存器时的延迟 */
#define ETH_REG_WRITE_DELAY     ((uint32_t)0x00000001)
/* LAN8720A LAN8742A 复位延迟 */ 
#define LAN8720A_RESET_DELAY    (PHY_RESET_DELAY)
#define LAN8742A_RESET_DELAY    (PHY_RESET_DELAY)
#else
/* PHY 复位延迟 */ 
#define PHY_RESET_DELAY         ((uint32_t)0x000FFFFF)
/* PHY 配置延迟 */ 
#define PHY_CONFIG_DELAY        ((uint32_t)0x00FFFFFF)
/* 写入以太网寄存器时的延迟 */
#define ETH_REG_WRITE_DELAY     ((uint32_t)0x0000FFFF)
/* LAN8720A LAN8742A 复位延迟 */ 
#define LAN8720A_RESET_DELAY    ((uint32_t)0x00FFFFFF)
#define LAN8742A_RESET_DELAY    ((uint32_t)0x00FFFFFF)
#endif

/*******************  PHY扩展寄存器部分 : ************************/
#define PHY_LAN8720A
/* 这些值与DP83848物理层芯片（PHY）相关，并且会因不同的物理层芯片而变化，因此用户必须根据所使用的外部物理层芯片来更新此值 */  

#ifdef PHY_LAN8720A
/* The LAN8720A PHY status register  */
#define ETHERNET_PHY_ADDRESS   (0x0001)
#define PHY_SR                 ((uint16_t)0x001F) /* PHY status register Offset */
#define PHY_SPEED_STATUS       ((uint16_t)0x0004) /* PHY Speed mask  1:10Mb/s       0:100Mb/s*/
#define PHY_DUPLEX_STATUS      ((uint16_t)0x0010) /* PHY Duplex mask 1:Full duplex  0:Half duplex*/
/* The LAN8720A PHY: Interrupt Mask Register (IMR) */
#define PHY_IMR                ((uint16_t)0x13)   /* Interrupt Mask Register */
#define PHY_IMR_LINK_INT_EN    ((uint16_t)0x0001) /* Enable Link Status Change Interrupt */
#define PHY_IMR_ANEG_DONE_INT_EN ((uint16_t)0x0002) /* Enable Auto-Negotiation Done Interrupt */
#define PHY_IMR_RX_ERR_INT_EN  ((uint16_t)0x0004) /* Enable Receive Error Interrupt */
#define PHY_IMR_TX_ERR_INT_EN  ((uint16_t)0x0008) /* Enable Transmit Error Interrupt */
#define PHY_IMR_ALL_INT_EN     ((uint16_t)0xFFFF) /* Enable All Interrupts */
/* The LAN8720A PHY: Interrupt Status Register (ISR) */
#define PHY_ISR                ((uint16_t)0x12)   /* Interrupt Status Register */
#define PHY_ISR_LINK_STATUS    ((uint16_t)0x0001) /* Link Status Change Indicator */
#define PHY_ISR_ANEG_DONE      ((uint16_t)0x0002) /* Auto-Negotiation Complete Indicator */
#define PHY_ISR_RX_ERR         ((uint16_t)0x0004) /* Receive Error Indicator */
#define PHY_ISR_TX_ERR         ((uint16_t)0x0008) /* Transmit Error Indicator */
#elif defined PHY_LAN8742A
/* The LAN8742A PHY status register  */
#define ETHERNET_PHY_ADDRESS   (0x0001)
#define PHY_SR                 ((uint16_t)0x001F) /* PHY status register Offset */
#define PHY_SPEED_STATUS       ((uint16_t)0x0004) /* PHY Speed mask  1:10Mb/s       0:100Mb/s*/
#define PHY_DUPLEX_STATUS      ((uint16_t)0x0010) /* PHY Duplex mask 1:Full duplex  0:Half duplex*/
/* The LAN8742A PHY: Interrupt Control (Mask) Register */
#define PHY_IMR                ((uint16_t)0x13)   /* Interrupt Mask Register */
#define PHY_IMR_LINK_INT_EN    ((uint16_t)0x0001) /* Enable Link Status Change Interrupt */
#define PHY_IMR_ANEG_DONE_INT_EN ((uint16_t)0x0002) /* Enable Auto-Negotiation Done Interrupt */
#define PHY_IMR_SPEED_CHNG_INT_EN ((uint16_t)0x0004) /* Enable Speed Change Interrupt */
#define PHY_IMR_DUPLEX_CHNG_INT_EN ((uint16_t)0x0008) /* Enable Duplex Change Interrupt */
#define PHY_IMR_ALL_INT_EN     ((uint16_t)0xFFFF) /* Enable All Interrupts */
/* The LAN8742A PHY: Interrupt Status Register */
#define PHY_ISR                ((uint16_t)0x12)   /* Interrupt Status Register */
#define PHY_ISR_LINK_STATUS    ((uint16_t)0x0001) /* Link Status Change Indicator */
#define PHY_ISR_ANEG_DONE      ((uint16_t)0x0002) /* Auto-Negotiation Complete Indicator */
#define PHY_ISR_SPEED_CHNG     ((uint16_t)0x0004) /* Speed Change Indicator */
#define PHY_ISR_DUPLEX_CHNG    ((uint16_t)0x0008) /* Duplex Change Indicator */
#elif defined PHY_DPB3848
/* The DP83848 PHY status register  */
#define ETHERNET_PHY_ADDRESS   (0x0001)
#define PHY_SR                 ((uint16_t)0x10)   /* PHY status register Offset */
#define PHY_SPEED_STATUS       ((uint16_t)0x0002) /* PHY Speed mask */
#define PHY_DUPLEX_STATUS      ((uint16_t)0x0004) /* PHY Duplex mask */

/* The DP83848 PHY: MII Interrupt Control Register  */
#define PHY_MICR               ((uint16_t)0x11)   /* MII Interrupt Control Register */
#define PHY_MICR_INT_EN        ((uint16_t)0x0002) /* PHY Enable interrupts */
#define PHY_MICR_INT_OE        ((uint16_t)0x0001) /* PHY Enable output interrupt events */

/* The DP83848 PHY: MII Interrupt Status and Misc. Control Register */
#define PHY_MISR               ((uint16_t)0x12)   /* MII Interrupt Status and Misc. Control Register */
#define PHY_MISR_LINK_INT_EN   ((uint16_t)0x0020) /* Enable Interrupt on change of link status */
#define PHY_LINK_STATUS        ((uint16_t)0x2000) /* PHY link status interrupt mask */
#endif /* PHY_DPB3848 */
/* 注意：通用PHY寄存器在stm32f4x7_eth.h文件中定义 */


#ifdef __cplusplus
}
#endif

#endif /* __STM32F4x7_ETH_CONF_H */


/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
